The present invention generally relates to a compensation of latency effects on memories.
Computer systems generally comprise more or less complex memory units for storing information, such as data or programs (sequences of instructions), on a temporary or permanent basis. The term xe2x80x98memoryxe2x80x99 as used herein shall refer to any storage device such as disks, tapes, semiconductor devices, or the like, and is not limited to a certain type of purposes or applications such as in microcomputers. The term xe2x80x98dataxe2x80x99 as used herein shall refer to any kind of information such as individual or collective data, programs, instructions, as well on a temporary or permanent basis.
An access onto a memory is normally composed of three basic operations: 1) Telling the memory what to do, for example, read a number of bytes from a location in the memory; 2) waiting for the memory to complete an access; and 3) receiving the read out data or writing data into the memory. The transfer at the system level can be broken down to three timing parameters: (a) address transport, (b) data access time and (c) data transport. The address transport can be defined as the time required to get a new address and any control into an interface of the memory. This transport time generally is a function of the memory interface only. The data access time can be defined as the time to perform a data access, i.e. the time required for the memory to access a certain data from the internal memory array or core. The data transport can be defined as the time required to move the data from or to the memory and generally depends on the bandwidth, or signaling rate of the memory interface.
An important application of memories, and in particular deep memories (i.e. memories with a large memory capacity), is in testing applications for testing e.g. integrated circuits (IC""s) or other electronic devices, such as the Hewlett-Packard HP 83000 Digital IC Test Systems. A typical testing unit comprises a tester circuit and a device under test (DUT), which can be an IC or any other electronic device. Details of such testing devices can e.g. be found in U.S. patent application Ser. No. 09/050,505, issued as U.S. Pat. No. 6,216,243, co-pending U.S. patent application Ser. No. 09/140,427, and in the issued U.S. Pat. Nos. 6,065,144 and 6,055,644, all of the same applicant. The tester circuit generally comprises a signal generating unit for generating and applying a stream of stimulus data to the DUT, a signal receiving unit for receiving a response on the stream of stimulus data from the DUT, and a signal analyzing unit for comparing the response with an expected data stream. Test data applied to the DUT is also called vector data or test vector and comprises one or more single individual vectors. Each individual vector may represent a signal state which is either to be applied at one or more inputs of the DUT or output by the DUT, at a given point in time. In a digital IC-Tester vectors are normally executed in a sequential stream with parts of varying length thereof being repeated a certain number of times.
In particular digital IC-testers have a growing need for fast and deep memory to store the test vectors that are necessary to stimulate the DUT and to evaluate its response. As the DUTs become more and more complex and have an increasing amount of gates to be tested, the vector sequences become accordingly huge. In order to provide those massive amounts of memory at a reasonable price, memory devices with a high memory density are usually used, which also allow for high vector rates to minimize the test execution time and also to be able to test the DUT at its intended operating speed. The memory technology with the highest memory density presently is the dynamic random access memory (DRAM) technology.
A general limitation of all memories is the so-called latency time, as the time interval between the instant at which an instruction control unit initiates a call for data and the instant at which the actual transfer of data begins, or in other words, the time needed to access the first data word at a random address. The latency time generally increases the data access time. The latency time is not a fixed value for a certain memory or type of memory, but depends on the actual data access. However, in most memories the latency time substantially is a constant value for most of the data accesses. For the sake of simplicity, the latency time shall be regarded the following as a constant value for a certain memory.
Although the physical time to internally access a certain type of memory might be the same, the differences between memory devices that may affect the latency time can be the speed at which an address and a (control) information can be moved to the memory device, and the speed at which data can be moved back to a controller.
In applications which require only sequential (or as a synonym: serial) accessing, such as reading or writing, onto memories, i.e. an access onto the memory (e.g. data is to be written into the memory) occurs sequentially (or serially) in successive physical positions from a first starting address, the latency time only appears for accessing the starting address. After the first data word of the serial data has been accessed within the latency time, the reading or writing operation of the sequential data successive to the first data word at the starting address can be executed with a memory speed which generally is much higher than the xe2x80x98speedxe2x80x99 to access the first data word and normally is the maximum speed supported by the memory. This operation is also called a first data accessing operation, i.e. accessing the first data word of a serial data. In general, the latency time occurs with every first data accessing operation. It is to be understood, that during this latency time no data is available and a running process requiring further data needs to wait for that further data.
FIG. 1 shows an example of a memory 10 comprising (amongst other data which is not indicated) a first serially stored data area 20 with data blocks 20a, 20b, and 20c, and a second serially stored data area 30 with data blocks 30a, 30b, 30c, and 30d, each stored in contiguous areas of the memory. The memory 10 is controlled by a processor 40 which accesses the memory 10 via a data connection 50, which does not represent a fixed physical connection, but an access line from and to respective data blocks of the memory 10, which might be embodied by any connecting means as known in the art. In the example of FIG. 1, the processor accesses data block 20a via the data connection 50.
When the entire sequentially stored data area 20 is to be read, the latency time occurs only for accessing the (first) data block 20a, as the first data accessing operation. After accessing the data block 20a, the further data blocks 20b and 20c can be read with the memory speed. Accordingly, when the data area 30 is to be read, the latency time occurs only for accessing the data block 30a, as the first data accessing operation. After accessing the data block 30a, the further data blocks 30b, 30c, and 30d can be read with the memory speed.
In case that after accessing (e.g. for reading or writing) a first serial data, e.g. data area 20 or parts thereof, a second serial data is to be accessed, e.g. data area 30 or parts thereof, the latency time occurs first for accessing the first data word of the first serial data, e.g. data block 20a, and then again for accessing the first data word of the second serial data, e.g. data block 30a. This operation is also called a jump operation, i.e. jumping from one serial data to another serial data. In general, the latency time occurs with every jump operation.
In case that accessing a serial data, e.g. data area 20 or parts thereof, has to be repeated, the latency occurs between each accessing of the serial data. This operation is also called a repeat operation, i.e. repeating accessing a serial data. In general, the latency time occurs with every repeat operation. Repeat operations are in most cases only used for reading data and not for writing data since writing the same data repeatedly in the same data area normally is not very meaningful.
Latency problems become important in applications, such as in tester or backup systems, wherein the latency time is not neglectable with respect to other accessing times, e.g for reading or writing data. Particularly in applications with many jump and/or repeat operations, the total time required for accessing all of the requested data might mainly depends on the latency time of the memory.
When a certain data amount is to be accessed, which is not sequentially stored but distributed on various positions of one or more memories, the latency time might occur several times for accessing the entire data amount and can severely increase a data collection time as the time required for accessing the entire data amount. It is clear that in case of a memory latency, the data collection time depends on the individual data amount to be accessed, and in particular on the numbers of first data accessing, repeat, and jump operations.
One obvious possibility to avoid latency problems simply is to use a memory with a reduced or almost zero latency time, such as a synchronous random access memory (SRAM). However, those memories are generally expensive and reveal a low memory density, so that they might not be applicable for applications requiring a great amount of data to be stored.
Another possibility to avoid latency problems could be by sorting and serially storing the requested data already while loading data into the memory instead of jumping between differently stored serial data blocks or repeating certain serially stored data blocks during an execution of the data. However, it is apparent that this approach leads to a severe overhead in memory resources and management for the system software.
A further possibility to avoid latency problems is to use a memory with a reduced or almost zero latency time only for repeat operations in a way that such data sequences to be repeated are stored completely in that memory before an operation. However, that possibility lacks in a reduced flexibility and high costs for the additional memory which needs to be sufficient to store the required data sequences to be repeated.
EP-A-0228332 discloses an automatic test system with a xe2x80x9ctrue tester-per-pinxe2x80x9d architecture. In FIG. 6, EP-A-0228332 depicts an apparatus for accessing a memory by means of a RAM data decoder and a cache memory. Programming a loop requires that the address of both the first and last instruction of the loop as well as the number of times the loop is to be repeated is stored in a memory address generator. For the very first loop of a test sequence, this information is provided to the memory address generator prior to the start of the test. When the memory address generator reaches the first address of the loop, it stores this instruction and all the following instructions in the cache memory until the last instruction in the loop is reached. When the last instruction in the loop is reached, the memory address generator will repeat the instruction stored in the cache memory for the number of times that it has been programmed. During the loop the RAM data decoder decodes the instructions arriving from the cache memory rather than instructions from the memory. Loops which are unrestricted in length can be utilised even though the number of instructions required for the loop will not fit into the cache memory. In this event, the RAM data decoder runs from the cache memory until the number of instructions in the cache memory run out, then it returns to the instructions in the memory to complete the loop. This overcomes the problem of needing instant access to the next instruction which cannot occur because of the rather long cycle times of DRAMs, as well as providing the necessary time to fetch and load the addresses a number of cycles for the next loop.
U.S. Pat. No. 4,216,533 discloses a pattern generation with a plurality of low-speed memories having stored therein a plurality of patterns and first and second high-speed memories of higher operating speed than the low speed memories. One of the first and second high-speed memories is read to obtain output patterns and, at the same time, the plurality of low-speed memories are simultaneously read and the read-out data are successively written in the other high-speed memory alternately with each other. Upon completion of pattern generation from the one high-speed memory, pattern generation from the other high-speed memory is achieved.
It is an object of the invention to reduce an impact of the memory latency time on access operations onto the memory. The object is solved by the features of the independent claims.
According to a first aspect of the invention, an impact of the memory latency time on repeat operations with a memory (10) is reduced by providing a repeat start buffer (100), connectable with the memory (10), for simultaneously buffering a beginning of a data sequence to be repeatedly accessed, while the data sequence is accessed for the first time of the repeated access and a repeat switching unit (110), connectable with the memory (10) and connected with the repeat start buffer (100), for switching between the memory (10) and the repeat start buffer (100). The repeat switching unit (110) is switchable to the repeat start buffer (100) for accessing the buffered beginning of the data sequence to be repeatedly accessed.
A repeated accessing of the memory (10) for reading and/or writing a data sequence can be accomplished by applying the steps of:
(a) during a first accessing cycle:
(a1) accessing the memory (10) and
(a2) buffering a beginning of the data sequence-in a repeat start buffer (100);
(b) during each successive accessing cycle:
(b1) accessing first the buffered beginning of the data sequence from the repeat start buffer (100),
(b2) setting a data connection to the memory (10) at an address successive to the buffered data sequence, and
(b3) accessing then further data from the memory (10).
According to a second aspect of the invention, an impact of the memory latency time on jump operations with a memory (10) is reduced by providing a first data buffer (200a) and a second data buffer (200b), each connectable with the memory (10) and for buffering data sequences, a jump switching unit (210), connected with the first data buffer (200a) and the second data buffer (200b), for switching between the first data buffer (200a) and the second data buffer (200b). The memory (10) is accessible for each one of the data buffers (200a,b) during an idle memory accessing time of the other one of the data buffers (200a,b) for buffering a beginning of a data sequence to be accessed successively.
A repeated accessing of different areas in a memory (10) can be accomplished by applying the steps of:
(a) reading or writing a first data sequence from or for a first area (20) by using a data connection (105);
(b) during an idle time of the data connection (105), buffering in a first data buffer (200b) a beginning of a second data sequence from or for a second area (30); and
(c) after jumping to the second area (30):
(c1) reading out the buffered beginning of the second data sequence from the first data buffer (200b),
(c2) setting the data connection (105) in the second area (30) on an address successive to the data sequence buffered in the first data buffer (200b), and
(c3) reading or writing further data of the second data sequence from or for the second area (30) by using the data connection (105).
The first and second aspects of the invention can also be combined allowing to reduce an impact of the memory latency time on repeat operations, jump operations, and/or combined repeat and jump operations. The repeat and/or jump operations can be used as well reading and/or for writing data.
By buffering the beginning of a data sequence to be repeated and/or to be accessed successive to a current access operation, the waiting time due to latency effects between successive accessing cycles/operations can be reduced or even be eliminated, dependent on the storage capacity of the respective applied buffer. The buffer storage capacity is therefore preferably in accordance with the expected latency time, and preferably with the maximum latency time of the memory, meaning that the latency time is covered by the data content of the buffer. This allows to provide a continuous or almost continuous data stream with a minimum of components and management overhead required and with a high flexibility. The buffering can be provided during the access operations and need not be prepared in advance.
The invention can be preferably used in a testing system, and in particular in an IC tester.